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PRELIMINARY TECHNICAL DATA
a
High Bandwidth CMOS 8-/10-/12-Bit Parallel Interface Multiplying DACs AD5424/AD5433/AD5445* Preliminary Technical Data
FUNCTIONAL BLOCK DIAGRAM
VDD AD5424/ AD5433/ AD5445 VREF R 8/10/12 BIT R-2R DAC RFB IOUT1 IOUT2
FEATURES +2.5 V to +5.5 V Supply Operation Fast Parallel Interface (10ns WR cycle) 10MHz Multiplying Bandwidth 10V Reference Input 20-Lead TSSOP and Chip Scale (4 x4mm) Packages 8, 10 and 12 Bit Current Output DACs Pin compatible 8, 10 & 12 Bit DACs in Chip Scale Guaranteed Monotonic Four Quadrant Multiplication Power On Reset Readback Function 5A typical Power Consumption APPLICATIONS Portable Battery Powered Applications Waveform Generators Analog Processing Instrumentation Applications Programmable Amplifiers and Attenuators Digitally-Controlled Calibration Programmable Filters and Oscillators Composite Video Ultrasound Gain, offset and Voltage Trimming
CS R/W
Power On Reset
DAC REGISTER
INPUT LATCH
GND
DB0
DB7/DB9/DB11
DATA INPUTS
GENERAL DESCRIPTION
The AD5424/AD5433/AD5445 are CMOS 8, 10 and 12-bit current output digital-to-analog converters (DACs) respectively. These devices operate from a +2.5 V to 5.5 V power supply, making them suited to battery powered applications and many other applications. These DACs utilize Data readback allowing the user to read the contents of the DAC register via the DB pins. On power-up, the internal register and latches are filled with zeros and the DAC outputs are at zero scale. As a result of manufacture on a CMOS sub micron process, they offer excellent four quadrant multiplication characteristics, with large signal multiplying bandwidths of up to 10MHz.
The applied external reference input voltage (VREF) determines the full scale output current. An integrated feedback resistor (RFB) provides temperature tracking and full scale voltage output when combined with an external I-toV precision amplifier. The AD5424 is available in small 20 lead CSP and 16 lead TSSOP packages, while the AD5433/AD5445 DACs are available in small 20-lead CSP and TSSOP packages.
PRODUCT HIGHLIGHTS
1. 2. 3.
10MHz Multiplying Bandwidth 4mm x 4mm Chip Scale Packages and small TSSOP packages. Low Voltage, Low Power Current Output DACs.
*US Patent Number 5,689,257
REV. PrH Dec 2002
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P Box 9106, Norwood, MA 02062-9106, U.S.A. .O. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
AD5424/AD5433/AD5445-SPECIFICATIONS1noted. DC performance measured with (V = 2.5 V to 5.5 V, V = +10 V, I 2 = O V. All specifications T to T unless otherwise
DD REF OUT MIN MAX
OP1177, AC performance with AD811 unless otherwise noted.)
Parameter STATIC PERFORMANCE AD5424 Resolution Relative Accuracy Differential Nonlinearity AD5433 Resolution Relative Accuracy Differential Nonlinearity AD5445 Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Error Temp Coefficient2 Output Leakage Current Output Voltage Compliance Range REFERENCE INPUT Reference Input Range VREF Input Resistance DIGITAL INPUTS/OUTPUT2 Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current, IIL Input Capacitance VDD = 4.5 V to 5.5 V Output Low Voltage, VOL Output High Voltage, VOH VDD = 2.5 V to 3.6 V Output Low Voltage, VOL Output High Voltage, VOH DYNAMIC PERFORMANCE2 Reference Multiplying BW Output Voltage Settling Time AD5424 AD5433 AD5445 Slew Rate Digital to Analog Glitch Impulse Multiplying Feedthrough Error Output Capacitance Digital Feedthrough Total Harmonic Distortion Output Noise Spectral Density SFDR performance Intermodulation Distortion POWER REQUIREMENTS Power Supply Range IDD Power Supply Sensitivity 2 2.5 5 -85 -85 25 72 TBD 5.5 10 0.001
2
Min
Typ
Max
Units
Conditions
8 0.5 1 10 1 1 12 2 1 2 5 10 50 TBD 10 10
Bits LSB LSB Bits LSB LSB
Guaranteed Monotonic
Guaranteed Monotonic
Bits LSB LSB Guaranteed Monotonic mV ppm FSR/C nA Data = 0000H, TA = 25C, IOUT1 nA Data = 0000H, IOUT1 V V k V V V A pF V V V V MHz MHz
8 1.7
12
Input resistance TC = -50ppm/C VDD = 2.5 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2.5 V to 2.7 V
0.8 0.7 1 10 0.4 VDD - 1 0.4 VDD - 0.5 10 TBD 20 25 30 100 3 TBD TBD TBD
ISINK = 200 A ISOURCE = 200 A ISINK = 200 A ISOURCE = 200 A VREF = 100 mV rms, DAC loaded all 1s VREF = 6 V rms, DAC loaded all 1s Measured to 1/2 LSB. RLOAD = 100, CLOAD = 15pF. DAC latch alternately loaded with 0s and 1s. 1 LSB change around Major Carry DAC latch loaded with all 0s. Reference = 10kHz. DAC Latches Loaded with all 0s DAC Latches Loaded with all 1s Feedthrough to DAC output with CS high and Alternate Loading of all 0s and all 1s. VREF = 6 V rms, All 1s loaded, f = 1kHz VREF = 5 V, Sinewave generated from digital code. @ 1kHz
-75 2 4
ns ns ns V/s nV-s dB pF pF nV-s dB dB nV/Hz dB dB V A %/%
Logic Inputs = 0 V or VDD VDD = 5%
NOTES 1 Temperature range is as follows: B Version: -40C to +105C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA Single Supply Operation (Biased Mode) AD5424/AD5433/AD5445
(VDD = 2.5 V to 5.5 V, VREF = +2 V, IOUT2 = 1 V. All specifications TMIN to TMAX unless otherwise noted. DC performance measured with OP1177, AC performance with AD811 unless otherwise noted.)
Parameter STATIC PERFORMANCE AD5424 Resolution Relative Accuracy Differential Nonlinearity AD5433 Resolution Relative Accuracy Differential Nonlinearity AD5445 Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Error Temp Coefficient2 Output Leakage Current Output Voltage Compliance Range REFERENCE INPUT Reference Input Range VREF Input Resistance DIGITAL INPUTS/OUTPUT2 Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current, IIL Input Capacitance VDD = 4.5 V to 5.5 V Output Low Voltage, VOL Output High Voltage, VOH VDD = 2.5 V to 3.6 V Output Low Voltage, VOL Output High Voltage, VOH DYNAMIC PERFORMANCE2 Reference Multiplying BW Output Voltage Settling Time AD5424 AD5433 AD5445 Slew Rate Digital to Analog Glitch Impulse Multiplying Feedthrough Error Output Capacitance Digital Feedthrough Total Harmonic Distortion Output Noise Spectral Density SFDR performance Intermodulation Distortion POWER REQUIREMENTS Power Supply Range IDD Power Supply Sensitivity 2 2.5 5 -85 -85 25 72 TBD 5.5 10 0.001
2
Min
Typ
Max
Units
Conditions
8 0.5 1 10 1 1 12 2 1 2 5 10 50 TBD tbd 10
Bits LSB LSB Bits LSB LSB
Guaranteed Monotonic
Guaranteed Monotonic
Bits LSB LSB Guaranteed Monotonic mV ppm FSR/C nA Data = 0000H, TA = 25C, I OUT1 nA Data = 0000H, IOUT1 V V k V V V A pF V V V V MHz MHz
8 1.7
12
Input resistance TC = -50ppm/C VDD = 2.5 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2.5 V to 2.7 V
0.8 0.7 1 10 0.4 VDD - 1 0.4 VDD - 0.5 10 TBD 15 22 30 100 3 TBD TBD TBD
ISINK = 200 A ISOURCE = 200 A ISINK = 200 A ISOURCE = 200 A VREF = 100 mV rms, DAC loaded all 1s VREF = 1 V rms, DAC loaded all 1s Measured to 1/2 LSB. RLOAD = 100, CLOAD = 15pF. DAC latch alternately loaded with 0s and 1s. 1 LSB change around Major Carry DAC latch loaded with all 0s. Reference = 10kHz. DAC Latches Loaded with all 0s DAC Latches Loaded with all 1s Feedthrough to DAC output with CS high and Alternate Loading of all 0s and all 1s. VREF = 2 Vp-p, 1V Bias, All 1s loaded, f = 1kHz VREF = 2 V, Sinewave generated from digital code. @ 1kHz
-75 2 4
ns ns ns V/s nV-s dB pF pF nV-s dB dB nV/Hz dB dB V A %/%
Logic Inputs = 0 V or VDD VDD = 5%
NOTES 1 Temperature range is as follows: B Version: -40C to +105C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA
AD5424/AD5433/AD5445-SPECIFICATIONS1 V to 5.5 TIMING CHARACTERISTICS1,2 (V = 2.5 noted.) V, V = +5 V, I otherwise
DD REF
OUT2
= O V. All specifications TMIN to TMAX unless
Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9
Limit at TMIN, TMAX 0 0 10 6 0 5 7 5 25 5 10
Units ns ns ns ns ns ns ns ns ns ns ns min min min min min min min typ max typ max
Conditions/Comments R/W to CS Setup Time R/W to CS Hold Time CS Low Time (Write Cycle) Data Setup Time Data Hold Time R/W high to CS low CS Min High Time Data Acess Time Bus Relinquish Time
NOTES 1 See Figure 1. Temperature range is as follows: B Version: -40C to +105C. Guaranteed by design and characterisation, not subject to production test. 2 All input signals are specified with tr =tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Digital Output timing measured with Load circuit in Figure 2. Specifications subject to change without notice.
R/W
t1
t2
t6
t2
t7
CS
t3 t4 t5 t8
DATA VALID
t9
DATA
DATA VALID
Figure 1. Timing Diagram.
200uA TO OUTPUT PIN
IOL VOH (MIN) + VOL (MAX)
CL 50pF 200uA IOH
2
Figure 2. Load Circuit for Data Output Timing Specifications
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PRELIMINARY TECHNICAL DATA AD5424/AD5433/AD5445
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25C unless otherwise noted)
VDD to GND -0.3 V to +7 V VREF, RFB to GND -12 V to +12 V IOUT1, IOUT2 to GND -0.3 V to +7 V -0.3V to VDD +0.3 V Logic Inputs & Output2 Operating Temperature Range Industrial (B Version) -40C to +105C Storage Temperature Range -65C to +150C Junction Temperature +150C 16 lead TSSOP JA Thermal Impedance 150C/W 143C/W 20 lead TSSOP JA Thermal Impedance 20 lead CSP JA Thermal Impedance 135C/W Lead Temperature, Soldering (10seconds) 300C IR Reflow, Peak Temperature (< 20 seconds) +235C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at DBx, CS and W/R, will be clamped by internal diodes. Current should be limited to the maximum ratings given.
ORDERING GUIDE
Model AD5424BRU AD5424BCP AD5433BRU AD5433BCP AD5445BRU AD5445BCP
Temperature Range -40 -40 -40 -40 -40 -40
o o
Package Description TSSOP (Thin Shrink Small Outline Package) CSP (Chip Scale Package) TSSOP (Thin Shrink Small Outline Package) CSP (Chip Scale Package) TSSOP (Thin Shrink Small Outline Package) CSP (Chip Scale Package)
Package Option RU-16 CP-20 RU-20 CP-20 RU-20 CP-20
C C o C o C o C o C
to to to to to to
+105 +105 +105 +105 +105 +105
o o
C C o C o C o C o C
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5424/AD5433/AD5445 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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PRELIMINARY TECHNICAL DATA AD5424/AD5433/AD5445
AD5424 PIN FUNCTION DESCRIPTION
Pin TSSOP 1 2 3 4-11 12 13 14 15 16
Mnemonic CSP 19 20 1 2-9 10-13 14 15 16 17 18 IOUT1 IOUT2 GND DB7-DB0 NC CS R/ W VDD VREF RFB
Function DAC Current Output. DAC Analog Ground. This pin should normally be tied to the analog ground of the system. Ground Pin. Parallel Data Bits 7 through 0. No internal connection Chip Select Input. Active Low. Used in conjunction with R/W to load parallel data to the input latch or to read data from the DAC register. Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with CS to readback contents of DAC Register. Positive power supply input. These parts can be operated from a supply of +2.5 V to +5.5 V. DAC reference voltage input terminal. DAC feedback resistor pin. Establish voltage output for the DAC by connecting to external amplifier output.
PIN CONFIGURATIONS TSSOP & CSP
20 IOUT2 19 IOUT1 18 RFB 17 VREF 16 VDD
GND DB7 DB6 DB5 DB4 1 2 3 4 5
PIN 1 INDICATOR
IOUT1 1 IOUT2 2 GND 3 DB7 4 DB6 5 DB5 6 DB4 7 DB3 8 AD5424 (Not to Scale)
16 RFB 15 VREF 14 VDD 13 R/W 12 CS 11 DB0(LSB) 10 DB1 9 DB2
AD5424
TOP VIEW
15 R/W 14 CS 13 NC 12 NC 11 NC
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DB3 6 DB2 7 DB1 8 DB0 9 NC 10
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PRELIMINARY TECHNICAL DATA AD5424/AD5433/AD5445
AD5433 PIN FUNCTION DESCRIPTION
Pin TSSOP 1 2 3 4-13 14, 15 16 17 18 19 20
Mnemonic CSP 19 20 1 2-11 12, 13 14 15 16 17 18 IOUT1 IOUT2 GND DB9-DB0 NC CS R/ W VDD VREF RFB
Function DAC Current Output. DAC Analog Ground. This pin should normally be tied to the analog ground of the system. Ground Pin. Parallel Data Bits 7 through 0. Not internally connected. Chip Select Input. Active Low. Used in conjunction with R/W to load parallel data to the input latch or to read data from the DAC register. Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with CS to readback contents of DAC Register. Positive power supply input. These parts can be operated from a supply of +2.5 V to +5.5 V. DAC reference voltage input terminal. DAC feedback resistor pin. Establish voltage output for the DAC by connecting to external amplifier output.
PIN CONFIGURATIONS TSSOP & CSP
IOUT1 1 IOUT2 2 GND 3 DB9 4 DB8 5 DB7 6 DB6 7 DB5 8 DB4 9 DB3 10 AD5433 (Not to Scale)
20 RFB 19 VREF 18 VDD 17 R/W 16 CS 15 NC
GND DB9 DB8 DB7 DB6
1 2 3 4 5
20 IOUT2 19 IOUT1 18 RFB 17 VREF 16 VDD
PIN 1 INDICATOR
AD5433
TOP VIEW
15 R/W 14 CS 13 NC 12 NC 11 DB0
13 DB0(LSB) 12 DB1 11 DB2
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DB5 6 DB4 7 DB3 8 DB2 9 DB1 10
14 NC
PRELIMINARY TECHNICAL DATA AD5424/AD5433/AD5445
AD5445 PIN FUNCTION DESCRIPTION
Pin TSSOP 1 2 3 4-15 16 17 18 19 20
Mnemonic CSP 19 20 1 2-13 14 15 16 17 18 IOUT1 IOUT2 GND DB11-DB0 CS R/ W VDD VREF RFB
Function DAC Current Output. DAC Analog Ground. This pin should normally be tied to the analog ground of the system. Ground Pin. Parallel Data Bits 7 through 0. Chip Select Input. Active Low. Used in conjunction with R/W to load parallel data to the input latch or to read data from the DAC register. Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with CS to readback contents of DAC Register. Positive power supply input. These parts can be operated from a supply of +2.5 V to +5.5 V. DAC reference voltage input terminal. DAC feedback resistor pin. Establish voltage output for the DAC by connecting to external amplifier output.
PIN CONFIGURATIONS TSSOP & CSP
20 IOUT2 19 IOUT1 18 RFB 17 VREF 16 VDD
IOUT1 1 IOUT2 2 GND 3 DB11 4 DB10 5 DB9 6 DB8 7 DB7 8 DB6 9 DB5 10 AD5445 (Not to Scale)
20 RFB 19 VREF 18 VDD 17 R/W 16 CS 15 DB0(LSB) 14 DB1 13 DB2 12 DB3 11 DB4
GND DB11 DB10 DB9 DB8
1 2 3 4 5
PIN 1 INDICATOR
AD5445
TOP VIEW
15 R/W 14 CS 13 DB0 12 DB1 11 DB2
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DB7 6 DB6 7 DB5 8 DB4 9 DB3 10
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PRELIMINARY TECHNICAL DATA AD5424/AD5433/AD5445
TERMINOLOGY Relative Accuracy
Intermodulation Distortion
Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale and is normally expressed in LSBs or as a percentage of full scale reading.
Differential Nonlinearity
The DAC is driven by two combinded sine waves references of frequencies fa and fb. Distortion products are produced at sum and difference frequencies of mfanfb where m, n = 0, 1, 2, 3... Intermodulation terms are those for which m or n is not equal to zero. The second order terms include (fa +fb) and (fa - fb) and the third order terms are (2fa + fb), (2fa -fb), (f+2fa + 2fb) and (fa 2fb). IMD is defined as IMD = 20log (rms sum of the sum and diff distortion products)
rms amplitude of the fundamental
Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB max over the operating temperature range ensures monotonicity.
Gain Error
Compliance Voltage Range
Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For these DACs, ideal maximum output is VREF - 1 LSB. Gain error of the DACs is adjustable to zero with external resistance.
Output Leakage Current
The maximum range of (output) terminal voltage for which the device will provide the specified characteristics.
GENERAL DESCRIPTION DAC Section
Output leakage current is current which flows in the DAC ladder switches when these are turned off. For the IOUT1 terminal, it can be measured by loading all 0s to the DAC and measuring the IOUT1 current. Minimum current will flow in the IOUT2 line when the DAC is loaded with all 1s
Output Capacitance
Capacitance from IOUT1 or IOUT2 to AGND.
Output Current Settling Time
The AD5424, AD5433 and AD5445 are 8, 10 and 12 bit current output DACs consisting of a standard inverting R2R ladder configuration. A simplified diagram for the 8Bit AD5424 is shown in Figure 3. The feedback resistor RFB has a value of R. The value of R is typically 10k (minimum 8k and maximum 12k). If IOUT1 and IOUT2 are kept at the same potential, a constant current flows in each ladder leg, regardless of digital input code. Therefore, the input resistance presented at VREF is always constant.
R
VREF
This is the amount of time it takes for the output to settle to a specified level for a full scale input change. For these devices, it is specifed with a 100 resistor to ground.
Digital to Analog Glitch lmpulse
R
2R S2
R
2R S3
2R S1
2R S8
2R
R
RFB A IOUTA IOUT B
The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-secs or nV-secs depending upon whether the glitch is measured as a current or voltage signal.
Digital Feedthrough
DAC DATA LATCHES AND DRIVERS
Figure 3. Simplified Ladder
When the device is not selected, high frequency logic activity on the device digital inputs is capacitivelly coupled through the device to show up as noise on the IOUT pins and subsequently into the following circuitry. This noise is digital feedthrough.
Multiplying Feedthrough Error
This is the error due to capacitive feedthrough from the DAC reference input to the DAC IOUT1 terminal, when all o0s are loaded to the DAC.
Harmonic Distortion
Access is provided to the VREF, RFB, IOUT1 and IOUT2 terminals of the DAC, making the device extremely versatile and allowing it to be configured in several different operating modes, for example, to provide a unipolar output, bipolar output or in single supply modes of operation. in unipolar mode or four quadrant multiplication in bipolar mode.
Unipolar Mode
The DAC is driven by an ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental value is the THD. Usually only the lower order harmonices are included, such as second to fifth. THD = 20log (V22 + V32 + V42 + V52)
V1
Using a single op amp, these devices can easily be configured to provide 2 quadrant multiplying operation or a unipolar output voltage swing as shown in Figure 4. When an output amplifier is connected in unipolar mode, the output voltage is given by: VOUT = -D x VREF Where D is the fractional representation of the digital word loaded to the DAC.
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PRELIMINARY TECHNICAL DATA AD5424/AD5433/AD5445
D = 0 to 256 (8-Bit AD5424) = 0 to 1024 (10-Bit AD5433) = 0 to 4096 (12-Bit AD5445)
VDD R2
Bipolar Operation
In some applications, it may be necessary to generate full 4-Quadrant multplying operation or a bipolar output swing. This can be easily accomplished by using another external amplifier and some external resistors as shown in Figure 5.
C1
VDD VREF R1 R/W CS VREF AD5424/33/45
RFB IOUT1 IOUT2
When VIN is an ac signal, the circuit performs fourquadrant multiplication.
VOUT = -D VREF
GND
Table II. shows the relationship between digital code and the expected output voltage for bipolar operation (AD5426, 8-Bit device).
Table II. Bipolar Code Table
NOTES: 1R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 2C1 PHASE COMPENSATION (10pF-15pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
DATA INPUTS
AGND
Digital Input 1111 1000 0000 0000 1111 0000 0001 0000
Analog Output (V) +V REF (127/128) 0 -V REF (127/128) -V REF (128/128)
Figure 4. Unipolar Operation
With a fixed 10 V reference, the circuit shown above will give an unipolar 0V to -10V output voltage swing. When VIN is an ac signal, the circuit performs two-quadrant multiplication. The following table shows the relationship between digital code and expected output voltage for unipolar operation. (AD5424, 8-Bit device).
Table I. Unipolar Code Table
Digital Input 1111 1000 0000 0000 1111 0000 0001 0000
Analog Output (V) -V REF (255/256) -VREF (128/256) = -VREF/2 -V REF (1/256) -VREF (0/256) = 0
R3 10k VDD VDD VREF AD5424/33/45 R/W CS RFB IOUT1 IOUT2 R2 C1 A1 R4 10k A2 VOUT = -VREF to +VREF R5 20k
R1 VREF 10V
GND
DATA INPUTS
AGND NOTES: 1R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC. 2MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4. 3C1 PHASE COMPENSATION (10pF-15pF) MAY BE REQUIRED IF A1/A2 IS A HIGH SPEED AMPLIFIER.
Figure 5. Bipolar Operation (4 Quadrant Multiplication)
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PRELIMINARY TECHNICAL DATA AD5424/AD5433/AD5445
Overview of AD54xx devices Part No Resolution #DACs INL AD5424 AD5425 AD5426 AD5432 AD5433 AD5443 AD5445 8 8 8 10 10 12 12 1 1 1 1 1 1 1 0.5 0.5 0.5 1 1 2 2 Settling Time Interface Package 20ns 20ns 20ns 25ns 25ns 30ns 30ns Parallel Serial Serial Serial Parallel Serial Parallel Features
RU-16, CP-20 10 MHz, 10 ns CS Pulse Width RM-10 Byte Load,10 MHz BW, 50 MHz Serial RM-10 10 MHz BW, 50 MHz Serial RM-10 10 MHz BW, 50 MHz Serial RU-20, CP-20 10 MHz, 10 ns CS Pulse Width RM-10 10 MHz BW, 50 MHz Serial RU-20, CP-20 10 MHz, 10 ns CS Pulse Width
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PRELIMINARY TECHNICAL DATA AD5424/AD5433/AD5445
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20 Lead CSP (CP-20)
0.157 (4.0) BSC SQ PIN 1 INDICATOR
0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.024 (0.60) 0.017 (0.42) 16 0.009 (0.24) 15 0.148 (3.75) BSC SQ 0.012 (0.30) 0.009 (0.23) 0.007 (0.18) 0.030 (0.75) 0.024 (0.60) 0.020 (0.50)
0.010 (0.25) MIN
BOTTOM VIEW 20 1
TOP VIEW
0.080 (2.25) 0.083 (2.10) SQ 0.077 (1.95)
11 10 6 5
12 o MAX 0.035 (0.90) MAX 0.033 (0.85) NOM SEATING PLANE 0.020 (0.50) BSC
0.028 (0.70) MAX 0.026 (0.65) NOM
0.080 (2.00) REF
0.008 (0.20) REF
0.002 (0.05) 0.0004 (0.01) 0.0 (0.0)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
16 Lead TSSOP (RU-16)
0.201 (5.10) 0.193 (4.90)
20 Lead TSSOP (RU-20)
0.260 (6.60) 0.252 (6.40)
9
16
20
11
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
0.177 (4.50) 0.169 (4.30)
1 8
1
10
0.006 (0.15) 0.002 (0.05)
PIN 1 0.0433 (1.10) MAX 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090)
0.006 (0.15) 0.002 (0.05)
PIN 1 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090)
0.256 (6.50) 0.246 (6.25)
SEATING PLANE
8 0
0.028 (0.70) 0.020 (0.50)
SEATING PLANE
0.0256 (0.65) BSC
0.0118 (0.30) 0.0075 (0.19)
8o 0o
0.028 (0.70) 0.020 (0.50)
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